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CXD2301Q
8-bit 30MSPS Video A/D Converter with Built-in Amplifier/Clamp For the availability of this product, please contact the sales office.
Description The CXD2301Q is an 8-bit CMOS A/D converter for video applications with built-in amplifier/syncclamp circuits. A maximum conversion rate of 30MSPS is attained at a low power consumption by adopting a 2-step parallel system. Features * Resolution: 8 bits 1/2LSB (DL) * Maximum sampling frequency: 30MSPS * Low power consumption: 120mW (at 30MSPS typ.) (Including reference current) * Standby function: 0.5mW power consumption in standby * Amplifier functions: Built-in 3x amplifier (15MHz band), 2-input selector function provided * Synchronous clamp function * Clamp ON/OFF function * Reference voltage self-bias circuit * TTL compatible output * 3V digital interface capability * Single 5V or dual 4.75/3.3V power supplies * Low input capacitance: 8pF * Reference impedance: 330 (typ.) Applications Wide range of application fields where high-speed A/D conversion is required such as in the digital systems of TVs, VCRs, etc. Structure Silicon gate CMOS IC 32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD 7 * Reference voltage VRT, VRB VDD +0.5 to VSS -0.5 * Input voltage (analog) VIN
V V
VDD +0.5 to VSS -0.5 V * Input voltage (digital) VIH, VIL VDD +0.5 to VSS -0.5 V * Output voltage (digital) VOH, VOL VDD +0.5 to VSS -0.5 V * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage IDVSS-AVSSI 0 to 100 mV Single power supply AVDD, DVDD 5.0 0.25 V Dual power supply AVDD 4.75 0.25 V DVDD 3.3 0.3 V * Reference input voltage VRB 0 to V VRT to 2.2 V * Analog input ADIN More than 1.2Vp-p * Clock pulse width TPWI 16 (min) ns 16 (min) ns TPWO * Operating ambient temperature Topr -20 to +75 C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E92Y50B4X-PK
CXD2301Q
Block Diagram
VIN2 VIN1 27 25 R R 3R
OPO 30
ADV 21
ADV 22
AVDD 26
TEST 19 (DVSS) SEL 4 CE 5 D0(LSB) 16 D1 15 D2 14 D3 13 D4 12 D5 11 D6 10 D7(MSB) 9 CLK 18 DVDD 17 DVSS 8 Upper data latch Lower data latch
RTS VBI Reference supply 23 VRT 1 VRB
Lower encoder (4 bit)
Lower sampling comparator (4 bit)
Lower encoder (4 bit)
Lower sampling comparator (4 bit)
29 ADIN 2 AVSS AVSS
Upper encoder (4 bit)
Upper sampling comparator (4 bit)
3 ADV
7 AVSS 28 AVSS 31 AVSS
Clock generator
A/D Converter Block
24 VREF
6
20
32
CLE CLP CCP
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CXD2301Q
Pin Description Pin No. Symbol Equivalent circuit
AVDD
Description Reference voltage (bottom) Connect to AVSS for normal use. When another external voltage is input, connect an external 0.1F capacitor and retain a 1.5V differential compared to the top reference voltage.
1
1
VRB
RTS 23
Rref
23
VRT
AVSS
Reference voltage (top) By setting VRB to AVSS, outputs approximately 1.5V. Connect only a 0.1F external by-pass capacitor for normal use. When another external voltage is input, it must be 2.2V or lower. Analog GND.
2, 3, 7, 28, 31 4
AVSS
AVDD 4 5
SEL
Switches the input of the 3x amplifier. When SEL is at Low level, VIN1 is selected. When SEL is at High level, VIN2 is selected. Standby function ON/OFF selector. In standby state when High.
DVSS
5 19
CE TEST
19 AVSS
Fix to VSS for normal use. When CLE = Low: Clamp functiion is enabled. When CLE = High: Clamp function is disabled, and only the normal A/D converter function is enabled. Clock input
CE
AVDD
6
CLE
6 18 20 AVSS
18 20 8
CLK CLP DVSS
Inputs the clamp pulse to Pin 20 (CLP). Clamps the High interval signal voltage. Digital GND.
9 to 16
D7 to D0
Di
D7 (MSB) to D0 (LSB) output Outputs Low level in standby. In operation, the phase of D7 to D0 output is inverted against the phase of ADIN.
17
DVDD
5V or 3.3V
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CXD2301Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD CE
21
ADV
21
AVSS
Short Pins 21 and 22, and connect 0.1F external capacitor.
AVDD
22
ADV
22
AVSS
AVDD
24
VREF
24
Clamp reference voltage input. Clamps so that the reference voltage and the clamp interval ADIN input signal are equal. The reference voltage is more than 0.5V.
AVSS
AVDD R11 R
25 27
VIN1 VIN2
200 25 27 AVSS
R12
Amplifier input pin. Biased internally at 1.9V (when AVDD = 5V) or at 1.8V (when AVDD = 4.75V). When in standby as well. When SEL is at Low level, VIN1 is selected for input; When SEL is at High level, VIN2 is selected for input.
26
AVDD
5V or 4.75V
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CXD2301Q
Pin No.
Symbol
Equivalent circuit
Description
AVDD
29
ADIN
29
A/D converter block analog input.
AVSS
AVDD
30
OPO
30
Amplifier output. The phase of this output is inverted against the phase of VIN1, 2. In standby mode, it becomes high-impedance output condition.
AVSS
AVDD
32
CCP
32
Integrates the clamp control voltage. The relationship between the CCP voltage variation and the ADIN voltage is positive phase.
AVSS
* The following table shows the status of the digital output pins when the TEST pin is used with the CE and SEL pins. TEST L L H H H CE L H L H H SEL X X X L H D1 D1 L H L D2 D2 L L H D3 D3 L H L D4 D5 D6 D6 L L H D7 D7 L H L D8 D8 L L H
D4 D5 L L TEST mode L H H L
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CXD2301Q
Digital Output The following table shows the correlation between the ADIN input voltage and the digital output code. Take notice that the phase of ADIN input signal voltage is inverted against the phase of the digital output. ADIN Input signal voltage VRT : : : : VRB Step 0 : 127 128 : 255 Digital output code MSB LSB 00000 : 01111 10000 : 11111 000 111 000 111
TPW1
TPW0
Clock 2V
ADIN input
N
N+1
N+2 N+1
N+3 N
N+4 N-1
Data output
N-3 Td
N-2
: Indicates point at which input signal is sampled
Fig. 1. Timing Chart
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CXD2301Q
Electrical Characteristics (1) When using a single power supply (Fc = 30MSPS, AVDD = DVDD = +5V, VRB = 0V, VRT = 1.5V, Ta = 25C) Item Supply current Standby supply current Max. conversion rate Min. conversion rate ADIN input band (at -1dB) ADIN input capacitance Symbol IAD + IDD ISTB Conditions Fc = 35MSPS NTSC ramp wave input CE = DVDD 30 0.5 20 VIN = 0.75V + 0.07Vrms 230 VRB = AVSS 1.38 -40 +25 3.5 0.5 DVDD = max. VIH = VDD VIL = 0V DVDD = min. VOH = VDD-0.5V VOL = 0.4V -1.1 3.7 7 -2.5 6.5 13 +0.5 0.3 1 0.5 30 2 VADIN = DC, PWS = 3sec VREF = 0.5V VREF = 1.5V 0 -40 +20 -20 25 DC to 15MHz VBI1, 2 RI1, 2 When open 19 8.5 9.5 1.9 27 15 35 10.5 +40 0 25 +1.3 0.5 5 5 8 330 1.52 -20 +45 440 1.66 0 +65 Min. Typ. 27 130 Max. 35 200 Unit mA A MSPS MHz pF V mV
Fc max VIN = 0 to 1.5V Fc min fIN = 1kHz ramp BW CADIN
Reference resistance (VRT to VRB) RREF Self bias Offset voltage VRT EOT EOB VIH VIL IIH IIL IOH IOL TDL EL ED DG DP taj tsd Eoc tcpd
Digital input voltage
V
Digital input current
A
Digital output current Output data delay Integral nonlinearity error Differential nonlinearity error Differential gain error Differential phase error Aperture jitter Sampling delay Clamp offset voltage Clamp pulse delay Amplifier gain VIN1 and VIN2 bias voltage VIN1 and VIN2 input resistance
mA ns LSB LSB % deg ps ns mV ns dB V k pF
With TTL 1gate and 10pF load Fc = 30MSPS VIN = 0 to 1.5V Fc = 30MSPS VIN = 0 to 1.5V NTSC 40IRE mod ramp, Fc = 14.3MSPS
VIN1 and VIN2 input capacitance CI1, 2
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CXD2301Q
(2) When using a dual power supply (Fc = 30MSPS, AVDD = 4.75V, DVDD = 3.3V, VRB = 0V, VRT = 1.5V, Ta = 25C) Item Analog supply current Digital supply current Standby supply current Max. conversion rate Min. conversion rate ADIN input band (at -1dB) ADIN input capacitance Symbol IAD IDD ISTB Conditions Fc = 30MSPS NTSC ramp wave input Fc = 30MSPS NTSC ramp wave input CE = DVDD 30 0.5 20 VIN = 0.75V + 0.07Vrms 230 VRB = AVSS 1.44 -40 +25 2.5 0.5 DVDD = max. VIH = DVDD VIL = 0V DVDD = min. VOH = VDD-0.5V VOL = 0.4V -1.1 3.7 7 -2.5 6.5 13 +0.5 0.3 1 0.5 30 2 VREF = 0.5V VIN = DC, PWS = 3sec VREF = 1.5V 0 -40 +20 -20 25 DC to 15MHz VBI1, 2 RI1, 2 CI1, 2 When open 19 8.5 9.5 1.8 27 15 35 10.5 +40 0 25 +1.3 0.5 5 5 8 330 1.52 -20 +45 440 1.6 0 +65 Min. Typ. 24 1 130 Max. 32 2 200 Unit mA mA A MSPS MHz pF V mV
Fc max VIN = 0 to 1.5V Fc min fIN = 1kHz ramp BW CADIN
Reference resistance (VRT to VRB) RREF Self bias Offset voltage VRT EOT EOB VIH VIL IIH IIL IOH IOL TDL EL ED DG DP taj tsd Eoc tcpd
Digital input voltage
V
Digital input current
A
Digital output current Output data delay Integral nonlinearity error Differential nonlinearity error Differential gain error Differential phase error Aperture jitter Sampling delay Clamp offset voltage Clamp pulse delay 3x amplifier gain VIN1 and VIN2 bias voltage VIN1 and VIN2 input resistance VIN1 and VIN2 input capacitance
mA ns LSB LSB % deg ps ns mV ns dB V k pF
With TTL 1gate and 10pF load Fc = 30MSPS VIN = 0 to 1.5V Fc = 30MSPS VIN = 0 to 1.5V NTSC 40IRE mod ramp, Fc = 14.3MSPS
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CXD2301Q
Application Circuit (1) When using the internal amplifier a) Clamp usage example (using self bias)
ACO4 CLOCK IN CK CLAMP PULSE IN +4.75V LATCH * Q 0.1 VREF 20k 0.1 25 0.1 VIDEO IN 75 29 0.1 10p 30 31 32 0.01 1 2 3 4 5 6 7 8 26 27 28 24 23 22 21 20 19 18 17 0.1
+3.3V
0.1
16 15 14 13 12 11 10 9
D0 D1 D2 D3 D4 D5 D6 D7
GND (analog)
GND (digital)
Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at this time.
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CXD2301Q
b) Digital clamp usage example (using self bias)
ACO4 CLOCK IN 0.1 0.1 +4.75V +3.3V
0.1
VIDEO IN1 VIDEO IN2
0.1 25 0.1 26 27 28 75 29 0.1 30 31 32
24
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9 Subtracter, Comparator, etc. Clamp Level Setting data
1
2
3
4
5
6
7
8
DAC, GND (analog) GND (digital) PWM, etc.
High impedance for all information outside the clamp interval
The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is positive phase. ADIN/VCCP = 3.0 (fs = 30MSPS)
- 10 -
CXD2301Q
c) When not using the clamp
+3.3V (digital) 0.1 ACO4 CLOCK IN 0.1 0.1
+4.75V
0.1 25 0.1 0.1 26 27 28 75 29 0.1 10p 30 31 32
24
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9 D0 D1 D2 D3 D4 D5 D6 D7
VIDEO IN
1
2
3
4
5
6
7
8 GND (digital)
GND (analog) +3.3V (digital)
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CXD2301Q
(2) When not using the internal amplifier a) Clamp usage example
+4.75V 20k ACO4 CLOCK IN CK Q 23 22 21 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 D0 D1 D2 D3 D4 D5 D6 D7 0.1 0.1 0.1 +3.3V (digital)
CLAMP PULSE IN
LATCH *
24 +4.75V (analog) 25 0.1 VIDEO IN # 10 75 28 29 10p 30 31 32 0.01 26 27
20
GND (analog)
GND (digital)
Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp operation. However, depending on the relationship between the sampling frequency and the clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at this time. # Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output" on page 6.)
- 12 -
CXD2301Q
b) Digital clamp usage example
{ 3.3V (digital) 0.1 ACO4 CLOCK IN 0.1 0.1
24 +4.75V (analog) 25 0.1 VIDEO IN # 10 75 28 29 10p 30 31 32 0.01 1 26 27
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9 Subtracter, Comparator, etc. Clamp Level Setting data
2
3
4
5
6
7
8
GND (analog)
GND (digital)
DAC, PWM, etc.
High impedance for all information outside the clamp interval
The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is positive phase. VADIN/VCCP = 3.0 (fs = 20MSPS) c) When not using the clamp
+3.3V (digital) 0.1 ACO4 CLOCK IN 0.1 0.1
24 +4.75V (analog) 25 0.1 VIDEO IN # 75 29 10p 30 31 32 1 26 27 28
23
22
21
20
19
18
17 16 15 14 13 12 11 10 9 D0 D1 D2 D3 D4 D5 D6 D7
2
3
4
5
6
7
8 GND (digital)
GND (analog) +3.3V (digital)
# Take care that the phase of ADIN input is inverted against the phase of the digital output, because the use of the built-in inverting amplifier is standard. (Refer to "Digital Output" on page 6.) - 13 -
CXD2301Q
Example of Representative Characteristics
-10 VDD=4.75V VIN=150mVrms -20 VIN1=GND -30
fIN=NTSC ramp wave VIN=150mVrms
Current consumption [mA]
Crosstalk [dB]
-40 -50 -60 -70 -80
30
20
1
5
10
50
0.1
0.5
1
5
10
fIN-Input frequency [MHz]
fs-Sampling frequency [MHz]
Input frequency of VIN2 vs. Crosstalk VIN2VIN1
Sampling frequency vs. Current consumption
VDD=5V, Input waveform is ramp wave VIN=150mVrms
Current consumption [mA]
40
30
20 0.1
0.5
1
5
10
50
fIN-Input frequency [MHz]
Input frequency vs. Current consumption
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CXD2301Q
8bit ADC and DAC Evaluation Board Evaluation boards are available for the high speed, low power consumption CMOS converters, CXD2301Q (8-bit 30MHz A/D) and CXD1171M (8-bit 40MHz D/A). The evaluation board is composed of a main board common to either type, to which is added sub board D2301Q or sub board D1171M. The junction is made through a socket. To the main board are mounted an input interface, clock buffer and latch. To each of the sub boards is mounted CXD2301Q and CXD1171M respectively. Those IC's are mounted according to recommended print patterns designed to provide maximum performance to the A/D and D/A converters. Block Diagram
V OUT
DAC SOCKET
ANALOG CIRCUIT MOUNT PORTION
8
DATA LATCH
V REF
DIGITAL CIRCUIT MOUNT PORTION
DAC SOCKET
V IN
ANALOG INPUT INTERFACE
8 4 CLOCK BUFFER
ANALOG CIRCUIT MOUNT PORTION
OSC SW
GND +5V
-5V
CLOCK OE SEL SYNC
CLE
BLK
Unnecessary at self bias use
Characteristics * Resolution * Maximum conversion rate * Digital input level * Supply voltage Supply Voltage Item +5V -5V Clock Input CMOS compatible Pulse width TCW1 TCW0 Min.
8bit 30MHz CMOS level 5.0V (Single +5V power supply possible at self bias use)
Typ.
Max. 165 20
Unit mA
16ns (min) 16ns (min)
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CXD2301Q
Analog Output (CXD1171M) Item Analog output Min. 1.8 Typ. 2.0
(RL > 10k) Max. 2.1 Unit V
Output Format (CXD2301Q) The table shows the output format of AD Converter Analog input voltage VRT : : : : VRB Timing Chart Step 0 : 127 128 : 255 Digital output code MSB LSB 00000 : 01111 10000 : 11111 000 111 000 111
Analog input
TPW0 External clock TPW1 Tdc tPD(AD) AD output tDD Latch output DA input tS DA clock th
AD clock
DA output
tPD(DA)
Item Clock High time Clock Low time Clock Delay Data delay AD Data delay (latch) Settling time Hold time Data delay DA
Symbol TPW1 TPW0 Tdc
Min. 16 16
Typ.
Max.
Unit ns ns
24 13 25 5 5 10 10 - 16 -
ns ns ns ns ns ns
tPD (AD) tDD tS th tPD (DA)
CMOS ADC/DAC Peripheral Circuit Board (Main Board)
DVSS DVDD
OUTPUT GAIN ADJUST 13 NC 14 NC 15 AVSS 16 AVSS BLK 9 CLK 9 10 74S174 7 11 (LATCH) 6 12 5 4 3 2 1 0.01 SW1 CLK 15 PW SYNC 14 SEL 13 CLK 12 DVDD 11 D7 10 D6 9 D5 8 D4 7 D3 6 D2 5 D1 4 D0 3 DVSS 2 OE 1 8 9 10 11 12 13 DVDD 0.01 DVDD DVSS 14 7 6 5 4 3 2 1 BLK OE SEL CLE SYNC OSC SWITCH EXT/INT R9 75 EXTERNAL CLOCK INPUT DVDD 15 14 13 12 11 6 5 4 3 1 7 DVSS OSC OUT 0.01 DVSS 8 14 DVDD 10 7 16 NC 17 NC 18 VRT 19 VRTS 20 AVDD 21 AVDD 22 VIN 23 AVSS 24 AVSS 25 VRBS 26 VRB 27 VREF 28 CLE 9 8 DVSS CLEAR 13 14 15 DVDD 16 8 DVSS D7 8 D6 7 D5 6 D4 5 D3 4 D2 3 D1 2 D0 1 17 IREF 18 VREF 19 AVDD 20 AVDD 21 IO 22 IO 23 NC 24 DVDD V OUT CLK 10 0.01 DVSS 11 NC 12
VR4 20k
R8 C5 3.3k
0.1 (16R)
VRB ADJUST
VRT ADJUST
AVDD
R4 510
VR2 2k
Q2
R7 200 (R)
VR1 2k
Q1
R6 510
R5 510
74S04 OR 74HC04 (INV BUFFER)
-5V +5V GND AVDD DVDD
- 17 -
AVSS
VIDEO INPUT
SW2
AVDD
C3 0.01
C3
Q3
R3 C2 10 75
C1 470 R1 100k
R2 75
2 CLEAR 74S174 16 (LATCH) 1
AVSS
C4 0.01
VR3 20k
SW3
CLAMP VOLTAGE ADJUST
47
(R IN=75) SYNC INT 47 VR5 20k R10 75
CXD2301Q
CXD2301Q
CMOS ADC/DAC Peripheral Circuit Board (Sub Board)
CLP 15 NC 16 NC 17 NC 18 NC 19 AVDD 20 AVDD 21 VIN 22 AVSS 23 AVSS 24 NC 25 NC 26 VREF 27 CLE 28 C5 1000p C6 1 C4 0.1 25 26 27 28 24
C3 0.01 C2 0.1 23 22 21 20 19 18 17 16 15 14 13 CXD2301Q 29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9 C1 0.1
14 NC 13 NC 12 CLK 11 DVDD 10 D7 9 8 7 6 5 4 3 2 1 D6 D5 D4 D3 D2 D1 D0 DVSS NC
NC 13 NC 14 AVSS 15 AVSS 16 IREF 17 C3 VREF 18 AVDD 19 AVDD 20 IO 21 IO 22 NC 23 DVDD 24 C2
13 14 15 16 17 18 19 20 21 22 23 24 CXD1171M
12 11 C4 10 9 8 7 6 5 4 3 2 1
12 NC 11 DVSS 10 CLK 9 8 7 6 BLK D7 D6 D5
5 D4 4 3 D3 D2
2 D1 1 D0
C1
- 18 -
CXD2301Q
List of Parts resitance R1 100k R2 75 R3 75 R4 510 R5 510 R6 510 R7 R = 200 R8 18R 3.3k R9 75 R10 75 VR1 2k VR2 2k VR3 20k VR4 20k VR5 20k capacitance C1 470F/6.3V (chemical) C2 10F/16V (chemical) C3 0.01F C4 0.01F C5 0.1F C6 0.1F C7 0.1F C8 0.1F C9 0.1F C10 0.1F C11 47F/10V (chemical) C12 47F/10V (chemical) C13 47F/10V (chemical) C14 0.1F
transistor Q1 Q2 Q3 ic IC1 IC2 IC3 oscillator OSC others connector SW
2SC2785 2SC2785 2SC2785
74S174 74S174 74S04
BNC071 AT1D2M3
Adjustment 1. Vref adjustment (VR1, VR2) Adjustment of A/D converter reference voltage. VRB is adjusted through VR1 and VRT through VR2. When self bias is used, there is no need for adjustment. Reference voltage is set through self bias at delivery. 2. Setting of clamp reference voltage (VR3) Clamp reference voltage is set. 3. DAC output full scale adjustment (VR4) Full scale voltage of D/A converter output is adjusted at the PCB shipment, the full scale voltage is adjusted to approx. 2V. 4. Sync (clamp) pulse interface (VR5) This adjustment enables interface with the signal generator and others at the PCB shipment, adjustment is performed to obtain a threshold of approx. 2.5V to an H sync of 0 to 5V. - 19 -
CXD2301Q
5. OE, SEL, Sync, BLK, CLE, Sync INT The following pins are set on the main board: Sync, CLE, Sync INT (CXD2301Q) and BLK (CXD1171M), OE, SEL (not used). For the pins function, refer to the specifications. The difference between Sync pin and Sync INT pin is that you input a pulse above 3.5Vp-p to Sync INT pin. The pulse threshold is set through VR5. For input through Sync pin, pulse is input at TTL or CMOS level. In this case cut off the junction line between Sync pin and Sync INT pin. At the PCB shipment the main board pins are set as follows. * OE ........ Low * SEL ...... Low * Sync ..... Line junction with Sync INT pin * CLE ...... Low (Clamp function ON) * BLK ...... Low (Blanking OFF) 6. Clamp pulse input method The clamp pulse is directly input to CXD2301Q as show in Application Circuit examples (1) and (2). Use the direct input that is set at the PCB shipment. Points on the PCB Pattern Layout 1. Set the layout not to have Digital current flow into Analog GND (Part 1). (For 1, see P.17 Component side diagram.) 2. At CXD2301Q sub board, C2 and C3 capacitors serve the important role of bringing out CXD2301Q's full performance. These are over 0.1F (ceramic) capacitors with good high frequency characteristics. Layout as close to the IC as possible. 3. Analog GND (AVSS) and Digital GND (DVSS) are on a common voltage and power source. Keeping ADC's DVSS (Part 2) as close as possible to the voltage supply source will provide better results. That is, a layout where ADC is close to the voltage supply source, is recommended. (For 2, see P.17 Component side diagram.) 4. ADC samples analog signals at the clock falling edge point. Accordingly clocks supplied to ADC should not have any jitter. 5. The PCB layout shows ADC and DAC's Analog GND independently from the voltage supply source. The layout aims at providing an independent evaluation of ADC and DAC, as much as possible. On the actual board, common use will not cause any problems.
- 20 -
CXD2301Q
Notes on Operation 1. Reference voltage By shorting VRT and VRTS, VRB and VRBS, CXD2301 has the self bias function that generates VRT = about 2.6V and VRB = about 0.5V. On the PCB, either self bias or the external reference voltage can be selected depending on the junction method of the jumper line. At shipment from the factory, reference voltage is provided in self bias. Also, to provide external reference voltage, adjust the dynamic range (VRT - VRB) to above 1.8Vp-p. 2. Clock input There are 2 modes for the PCB clock input. 1) Provided from the external signal generator (External clock) 2) Using the crystal oscillator (built-in clock driver). (Internal clock) The 2 modes are selected using the switch on the PCB. 3. The 2 Latch IC's (74S174) are not absolutely necessary for the evaluation of ADC and DAC. That is, operation will still be normal if ADC output data is directly input to DAC input. However, as ADC output data is hardly ever D/A converted without executing Digital signal processing, it was mounted to indicate an example layout of Digital signal processing IC. When the ADC output data is used, use the output of the latch IC. 4. When clamp is not used Turning CLE to H will set OFF the clamp function. In this case, the DC element is cut off by means of C2 on the main board and DC voltage on the ADC side of C2 turns to about (VRT + VRB). To transfer DC elements of input signals, short C2. At that time, it is necessary to bias input signals, but keeping R2 open, Q3 can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch On the evaluation board, the clamp pulse is latched with ADC sampling CLK and then input to the CLP pin. This is to minimize Vsag due the synchronizing of noise and clamp pulse beat elements with GND sampling clock around ADC. If there are no problems with Vsag, latch is not necessary. 6. Peripheral through hole There is a group of through holes on the Analog input, output and Logic. These are to be used when mounting additional circuits to the PCB. Use when necessary. The connector hole on DAC part is used to mount the test chassis and the mount jack.
- 21 -
CXD2301Q
Silk Side
Component Side
Soldering Side (Diagram seen from the component side)
- 22 -
CXD2301Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 0.2 + 0.3 7.0 - 0.1 24 17 + 0.35 1.5 - 0.15
0.1
25
16
32
9
+ 0.2 0.1 - 0.1
1 0.8 + 0.15 0.3 - 0.1
8 + 0.1 0.127 - 0.05 0 to 10
0.12 M
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32P-L01 QFP032-P-0707-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g
- 23 -
0.50
(8.0)

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